View LTC2484CDDPBF_4367374.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc2484 1 2484fd typical application features applications description 24-bit ? adc with easy drive input current cancellation the ltc ? 2484 combines a 24-bit no latency ? ? analog- to-digital converter with patented easy drive? technology. the patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. this allows large external source impedances and input signals with rail-to-rail input range to be directly digitized while maintaining exceptional dc accuracy. the ltc2484 includes an on-chip temperature sensor and oscillator. the ltc2484 can be con? gured to measure an external signal or internal temperature sensor and reject line frequencies. 50hz, 60hz or simultaneous 50hz/60hz line frequency rejection can be selected as well as a 2 speed-up mode. the ltc2484 allows a wide common mode input range (0v to v cc ) independent of the reference voltage. the reference can be as low as 100mv or can be tied directly to v cc . the ltc2484 includes an on-chip trimmed oscil- lator, eliminating the need for external crystals or oscil- lators. absolute accuracy and low drift are automatically maintained through continuous, transparent, offset and full-scale calibration. n easy drive technology enables rail-to-rail inputs with zero differential input current n directly digitizes high impedance sensors with full accuracy n 600nv rms noise n integrated temperature sensor n gnd to v cc input/reference common mode range n programmable 50hz, 60hz or simultaneous 50hz/60hz rejection mode n 2ppm inl, no missing codes n 1ppm offset and 15ppm total unadjusted error n selectable 2 speed mode (15hz using internal oscillator) n no latency: digital filter settles in a single cycle n single supply 2.7v to 5.5v operation n internal oscillator n available in a tiny (3mm 3mm) 10-lead dfn package n direct sensor digitizer n weight scales n direct temperature measurement n strain gauge transducers n instrumentation n industrial process control n dvms and meters l , lt, ltc and ltm, linear technology and the linear logo are registered trademarks and no latency ? and easy drive are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. patents pending. ltc2484 v ref v cc v cc gnd f o 1f sdo 4-wire spi interface 0.1f 10k i diff = 0 10k 0.1f sck 2484 ta01 cs sdi sense v in + v in C r source () 1 +fs error (ppm) C20 0 20 1k 100k 2484 ta02 C40 C60 C80 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c in = 1f +fs error vs r source at in + and in C
ltc2484 2 2484fd absolute maximum ratings supply voltage (v cc ) to gnd ...................... C0.3v to 6v analog input voltage to gnd ....... C0.3v to (v cc + 0.3v) reference input voltage to gnd .. C0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C0.3v to (v cc + 0.3v) digital output voltage to gnd ...... C0.3v to (v cc + 0.3v) operating temperature range ltc2484c ............................................... 0c to 70c ltc2484i ............................................ C40c to 85c storage temperature range .................. C65c to 125c (note 1) electrical characteristics (normal speed) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1 v ref v cc , Cfs v in +fs (note 5) l 24 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) l 2 1 10 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in C v cc (note 14) l 0.5 2.5 v offset error drift 2.5v v ref v cc , gnd in + = in C v cc 10 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref l 25 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref l 25 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref /c total unadjusted error 5v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 15 ppm of v ref ppm of v ref ppm of v ref output noise 5v v cc 5.5v, v ref = 5v, gnd in C = in + v cc (note 13) 0.6 v rms internal ptat signal t a = 27c 420 mv internal ptat temperature coef? cient 1.4 mv/c pin configuration top view 11 gnd dd package 10-lead (3mm s 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 f o sck gnd sdo cs sdi v cc v ref in + in C t jmax = 125c, ja = 43c/w exposed pad (pin 11) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc2484cdd#pbf ltc2484cdd#trpbf lbss 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2484idd#pbf ltc2484idd#trpbf lbss 10-lead (3mm 3mm) plastic dfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a la bel on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc2484 3 2484fd parameter conditions min typ max units resolution (no missing codes) 0.1 v ref v cc , Cfs v in +fs (note 5) l 24 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) l 2 1 10 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in C v cc (note 14) l 0.5 2 mv offset error drift 2.5v v ref v cc , gnd in + = in C v cc 100 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref l 25 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref l 25 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref /c output noise 5v v cc 5.5v, v ref = 5v, gnd in C = in + v cc (note 13) 0.84 v rms converter characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4) parameter conditions min typ max units input common mode rejection dc 2.5v v ref v cc , gnd in C = in + v cc (note 5) l 140 db input common mode rejection 50hz 2% 2.5v v ref v cc , gnd in C = in + v cc (note 5) l 140 db input common mode rejection 60hz 2% 2.5v v ref v cc , gnd in C = in + v cc (note 5) l 140 db input normal mode rejection 50hz 2% 2.5v v ref v cc , gnd in C = in + v cc (notes 5, 7) l 110 120 db input normal mode rejection 60hz 2% 2.5v v ref v cc , gnd in C = in + v cc (notes 5, 8) l 110 120 db input normal mode rejection 50hz/60hz 2% 2.5v v ref v cc , gnd in C = in + v cc (notes 5, 9) l 87 db reference common mode rejection dc 2.5v v ref v cc , gnd in C = in + v cc (note 5) l 120 140 db power supply rejection dc v ref = 2.5v, in C = in + = gnd 120 db power supply rejection, 50hz 2% v ref = 2.5v, in C = in + = gnd (note 7) 120 db power supply rejection, 60hz 2% v ref = 2.5v, in C = in + = gnd (note 8) 120 db analog input and reference the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units in + absolute/common mode in + voltage gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage gnd C 0.3v v cc + 0.3v v fs full-scale of the differential input (in + C in C ) l 0.5v ref v lsb least signi? cant bit of the output code l fs/2 24 v in input differential voltage range (in + C in C ) l Cfs +fs v v ref reference voltage range l 0.1 v cc v electrical characteristics (2x speed) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4)
ltc2484 4 2484fd analog input and reference the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units c s (in + )in + sampling capacitance 11 pf c s (in C )in C sampling capacitance 11 pf c s (v ref )v ref sampling capacitance 11 pf i dc_leak (in + )in + dc leakage current sleep mode, in + = gnd l C10 1 10 na i dc_leak (in C )in C dc leakage current sleep mode, in C = gnd l C10 1 10 na i dc_leak (v ref )v ref dc leakage current sleep mode, v ref = v cc l C100 1 100 na digital inputs and digital outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage cs , f o , sdi 2.7v v cc 5.5v (note 16) l v cc C 0.5 v v il low level input voltage cs , f o , sdi 2.7v v cc 5.5v l 0.5 v v ih high level input voltage sck 2.7v v cc 5.5v (note 10) l v cc C 0.5 v v il low level input voltage sck 2.7v v cc 5.5v (note 10) l 0.5 v i in digital input current cs , f o , sdi 0v v in v cc l C10 10 a i in digital input current sck 0v v in v cc (note 10) l C10 10 a c in digital input capacitance cs , f o , sdi 10 pf c in digital input capacitance sck 10 pf v oh high level output voltage sdo i o = C800a l v cc C 0.5 v v ol low level output voltage sdo i o = 1.6ma l 0.4 v v oh high level output voltage sck i o = C800a l v cc C 0.5 v v ol low level output voltage sck i o = 1.6ma l 0.4 v i oz hi-z output leakage sdo l C10 10 a power requirements the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode (note 12) sleep mode (note 12) l l 160 1 250 2 a a
ltc2484 5 2484fd timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units f eosc external oscillator frequency range (note 15) l 10 4000 khz t heo external oscillator high period l 0.125 100 s t leo external oscillator low period l 0.125 100 s t conv_1 conversion time for 1x speed mode 50hz mode 60hz mode simultaneous 50hz/60hz mode l l l 157.2 131.0 144.1 160.3 133.6 146.9 163.5 136.3 149.9 ms ms ms external oscillator l 41036/f eosc (in khz) ms t conv_2 conversion time for 2x speed mode 50hz mode 60hz mode simultaneous 50hz/60hz mode l l l 78.7 65.6 72.2 80.3 66.9 73.6 81.9 68.2 75.1 ms ms ms external oscillator l 20556/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 10) external oscillator (notes 10, 11) 38.4 f eosc /8 khz khz d isck internal sck duty cycle (note 10) l 45 55 % f esck external sck frequency range (note 10) l 4000 khz t lesck external sck low period (note 10) l 125 ns t hesck external sck high period (note 10) l 125 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 10, 12) l 0.81 0.83 0.85 ms external oscillator (notes 10, 11) l 256/f eosc (in khz) ms t dout_esck external sck 32-bit data output time (note 10) l 32/f esck (in khz) ms t 1 cs to sdo low l 0200ns t 2 cs to sdo hi-z l 0200ns t 3 cs to sck (note 10) l 0200ns t4 cs to sck (note 10) l 50 ns t kqmax sck to sdo valid l 200 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns t 7 sdi setup before sck (note 5) l 100 ns t 8 sdi hold after sck (note 5) l 100 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise speci? ed. v refcm = v ref /2, fs = 0.5v ref v in = in + C in C , v in(cm) = (in + + in C )/2 note 4: use internal conversion clock or external conversion clock source with f eosc = 307.2khz unless otherwise speci? ed. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: 50hz mode (internal oscillator) or f eosc = 256khz 2% (external oscillator). note 8: 60hz mode (internal oscillator) or f eosc = 307.2khz 2% (external oscillator). note 9: simultaneous 50hz/60hz mode (internal oscillator) or f eosc = 280khz 2% (external oscillator). note 10: the sck can be con? gured in external sck mode or internal sck mode. in external sck mode, the sck pin is used as digital input and the driving clock is f esck . in internal sck mode, the sck pin is used as digital output and the output clock signal during the data output is f isck . note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses the internal oscillator. note 13: the output noise includes the contribution of the internal calibration operations. note 14: guaranteed by design and test correlation. note 15: refer to applications information section for performance vs data rate graphs. note 16: for v cc < 3v, v ih is 2.5v for pin f o .
ltc2484 6 2484fd typical performance characteristics integral nonlinearity (v cc = 5v, v ref = 5v) integral nonlinearity (v cc = 5v, v ref = 2.5v) integral nonlinearity (v cc = 2.7v, v ref = 2.5v) total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) noise histogram (6.8sps) noise histogram (7.5sps) long-term adc readings input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C1.5 C0.5 0.5 1.5 2484 g01 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c C45c 25c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2484 g02 1.25 C1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd C45c, 25c, 90c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2484 g03 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd C45c, 25c, 90c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C1.5 C0.5 0.5 1.5 2484 g04 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c 25c C45c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C0.75 C0.25 0.25 0.75 2484 g05 1.25 C1.25 v cc = 5v v ref = 5v v in(cm) = 1.25v f o = gnd 85c 25c C45c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C0.75 C0.25 0.25 0.75 2484 g06 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c C45c output reading (v) C3 number of readings (%) 8 10 12 0.6 2484 g07 6 4 C1.8 C0.6 C2.4 1.2 C1.2 0 1.8 2 0 14 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v t a = 25c rms = 0.60v average = C0.69v output reading (v) C3 number of readings (%) 8 10 12 0.6 2484 g08 6 4 C1.8 C0.6 C2.4 1.2 C1.2 0 1.8 2 0 14 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v t a = 25c rms = 0.59v average = C0.19v time (hours) 0 C5 adc reading (v) C3 C1 1 10 20 30 40 2484 g09 50 3 5 C4 C2 0 2 4 60 v cc = 5v, v ref = 5v, v in = 0v, v in(cm) = 2.5v t a = 25c, rms noise = 0.60v
ltc2484 7 2484fd typical performance characteristics rms noise vs input differential voltage rms noise vs v in(cm) rms noise vs temperature (t a ) rms noise vs v cc rms noise vs v ref offset error vs v in(cm) offset error vs temperature offset error vs v cc offset error vs v ref input differential voltage (v) 0.4 rms noise (ppm of v ref ) 0.6 0.8 1.0 0.5 0.7 0.9 C1.5 C0.5 0.5 1.5 2484 g10 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(cm) (v) C1 rms noise (v) 0.8 0.9 1.0 24 2484 g11 0.7 0.6 01 356 0.5 0.4 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd t a = 25c temperature (c) C45 0.4 rms noise (v) 0.5 0.6 0.7 0.8 1.0 C30 C15 15 0304560 2484 g12 75 90 0.9 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd v cc (v) 2.7 rms noise (v) 0.8 0.9 1.0 3.9 4.7 2484 g13 0.7 0.6 3.1 3.5 4.3 5.1 5.5 0.5 0.4 v ref = 2.5v v in = 0v v in(cm) = gnd t a = 25c v ref (v) 0 0.4 rms noise (v) 0.5 0.6 0.7 0.8 0.9 1.0 1234 2484 g14 5 v cc = 5v v in = 0v v in(cm) = gnd t a = 25c v in(cm) (v) C1 offset error (ppm of v ref ) 0.1 0.2 0.3 24 2484 g15 0 C0.1 01 356 C0.2 C0.3 v cc = 5v v ref = 5v v in = 0v t a = 25c temperature (c) C45 C0.3 offset error (ppm of v ref ) C0.2 0 0.1 0.2 C15 15 30 90 2484 g16 C0.1 C30 0 45 60 75 0.3 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.7 offset error (ppm of v ref ) 0.1 0.2 0.3 3.9 4.7 2484 g17 0 C0.1 3.1 3.5 4.3 5.1 5.5 C0.2 C0.3 ref + = 2.5v ref C = gnd v in = 0v v in(cm) = gnd t a = 25c v ref (v) 0 C0.3 offset error (ppm of v ref ) C0.2 C0.1 0 0.1 0.2 0.3 1234 2484 g18 5 v cc = 5v ref C = gnd v in = 0v v in(cm) = gnd t a = 25c
ltc2484 8 2484fd typical performance characteristics temperature sensor vs temperature temperature sensor error vs temperature on-chip oscillator frequency vs temperature on-chip oscillator frequency vs v cc psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc conversion current vs temperature sleep mode current vs temperature temperature (c) C60 v ptat /v ref (v) 0.35 0.40 120 2484 g19 0.30 0.20 30 090 C30 60 0.25 v cc = 5v v ref = 1.4v f o = gnd temperature (c) C60 temperature error (c) 1 3 5 60 2484 g20 C1 C3 0 2 4 C2 C4 C5 C30 0 30 90 120 v cc = 5v f o = gnd v ref = 1.4v temperature (c) C45 C30 300 frequency (khz) 304 310 C15 30 45 2484 g21 302 308 306 15 0 60 75 90 v cc = 4.1v v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.5 300 frequency (khz) 302 304 306 308 310 3.0 3.5 4.0 4.5 2484 g22 5.0 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd frequency at v cc (hz) 1 0 C20 C40 C60 C80 C100 C120 C140 1k 100k 2484 g23 10 100 10k 1m rejection (db) v cc = 4.1v dc v ref = 2.5v in + = gnd in C = gnd f o = gnd t a = 25c frequency at v cc (hz) 0 C140 rejection (db) C120 C80 C60 C40 0 20 100 140 2484 g24 C100 C20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v v ref = 2.5v in + = gnd in C = gnd f o = gnd t a = 25c frequency at v cc (hz) 30600 C60 C40 0 30750 2484 g25 C80 C100 30650 30700 30800 C120 C140 C20 rejection (db) v cc = 4.1v dc 0.7v v ref = 2.5v in + = gnd in C = gnd f o = gnd t a = 25c temperature (c) C45 100 conversion current (a) 120 160 180 200 C15 15 30 90 2484 g26 140 C30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd cs = gnd sck = nc sdo = nc sdi = gnd temperature (c) C45 0 sleep mode current (a) 0.2 0.6 0.8 1.0 2.0 1.4 C15 15 30 90 2484 g27 0.4 1.6 1.8 1.2 C30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd cs = v cc sck = nc sdo = nc sdi = gnd
ltc2484 9 2484fd typical performance characteristics conversion current vs output data rate integral nonlinearity (2x speed mode; v cc = 5v, v ref = 5v) integral nonlinearity (2x speed mode; v cc = 5v, v ref = 2.5v) integral nonlinearity (2x speed mode; v cc = 2.7v, v ref = 2.5v) noise histogram (2x speed mode) offset error vs v in(cm) (2x speed mode) offset error vs temperature (2x speed mode) output data rate (readings/sec) 0 supply current (a) 500 450 400 350 300 250 200 150 100 80 2484 g28 20 40 60 100 70 10 30 50 90 v cc = 5v v cc = 3v v ref = v cc in + = gnd in C = gnd sck = nc sdo = nc sdi = gnd cs gnd f o = ext osc t a = 25c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C1.5 C0.5 0.5 1.5 2484 g29 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 25c, 90c C45c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2484 g30 1.25 C1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd 90c C45c, 25c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2484 g31 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 90c C45c, 25c output reading (v) 179 number of readings (%) 8 10 12 186.2 2484 g32 6 4 181.4 183.8 188.6 2 0 16 14 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v gain = 256 t a = 25c rms = 0.86v average = 0.184mv rms noise vs v ref (2x speed mode) v ref (v) 0 rms noise (v) 0.6 0.8 1.0 4 2484 g33 0.4 0.2 0 1 2 3 5 v cc = 5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c v in(cm) (v) C1 180 offset error (v) 182 186 188 190 200 194 1 3 4 2484 g34 184 196 198 192 0 2 5 6 v cc = 5v v ref = 5v v in = 0v f o = gnd t a = 25c temperature (c) C45 offset error (v) 200 210 220 75 2484 g35 190 180 160 C15 15 45 C30 90 0 30 60 170 240 230 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd
ltc2484 10 2484fd typical performance characteristics offset error vs v cc (2x speed mode) offset error vs v ref (2x speed mode) psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode) v cc (v) 2 2.5 0 offset error (v) 100 250 3 4 4.5 2484 g36 50 200 150 3.5 5 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c v ref (v) 0 offset error (v) 190 200 210 3 5 2484 g37 180 170 160 12 4 220 230 240 v cc = 5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c frequency at v cc (hz) 1 0 C20 C40 C60 C80 C100 C120 C140 1k 100k 2484 g38 10 100 10k 1m rejection (db) v cc = 4.1v dc ref + = 2.5v ref C = gnd in + = gnd in C = gnd f o = gnd t a = 25c frequency at v cc (hz) 0 C140 rejection (db) C120 C80 C60 C40 0 20 100 140 2484 g39 C100 C20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v ref + = 2.5v ref C = gnd in + = gnd in C = gnd f o = gnd t a = 25c frequency at v cc (hz) 30600 C60 C40 0 30750 2484 g40 C80 C100 30650 30700 30800 C120 C140 C20 rejection (db) v cc = 4.1v dc 0.7v ref + = 2.5v ref C = gnd in + = gnd in C = gnd f o = gnd t a = 25c pin functions sdi (pin 1): serial data input. this pin is used to select the line frequency rejection, input, temperature sensor and 2x speed mode. data is shifted into the sdi pin on the rising edge of serial clock (sck). v cc (pin 2): positive supply voltage. bypass to gnd (pin 8) with a 1f tantalum capacitor in parallel with 0.1f ceramic capacitor as close to the part as possible. v ref (pin 3): positive reference input. the voltage on this pin can have any value between 0.1v and v cc . the negative reference input is gnd (pin 8). in + (pin 4), in C (pin 5): differential analog inputs. the volt- age on these pins can have any value between gnd C 0.3v and v cc + 0.3v. within these limits the converter bipolar input range (v in = in + C in C ) extends from C0.5 ? v ref to
ltc2484 11 2484fd pin functions 0.5 ? v ref . outside this input range the converter produces unique overrange and underrange output codes. cs (pin 6): active low chip select. a low on this pin enables the digital input/output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 7): three-state digital output. during the data output period, this pin is used as the serial data output. when the chip select, cs , is high ( cs = v cc ), the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. gnd (pin 8): ground. shared pin for analog ground, digital ground and reference ground. should be connected directly to a ground plane through a minimum impedance. sck (pin 9): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as the digital output for the internal serial interface clock during the data input/output period. in external serial clock operation mode, sck is used as the digital input for the external se- rial interface clock during the data output period. a weak internal pull-up is automatically activated in internal serial clock operation mode. the serial clock operation mode is determined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs . f o (pin 10): frequency control pin. digital input that controls the conversion clock. when f o is connected to gnd the converter uses its internal oscillator running at 307.2khz. the conversion clock may also be overridden by driving the f o pin with an external clock in order to change the output rate or the digital ? lter rejection null. exposed pad (pin 11): this pin is ground and should be soldered to the pcb, gnd plane. for prototyping purposes this pin may remain ? oating. functional block diagram 1 9 4 5 8 7 6 3rd order $3 adc ref + in + in + 3 2 v ref v cc gnd in C in C ref C serial interface temp sensor mux sdi cs 2484 fb sck sd0 autocalibration and control internal oscillator
ltc2484 12 2484fd timing diagrams timing diagram using internal sck cs sdo sck sdi t 1 t 3 t 7 t 8 sleep t kqmax conversion data in/out t kqmin t 2 2484 td1 timing diagram using external sck cs sdo sck sdi t 1 t 5 t 6 t 4 t 7 t 8 sleep t kqmax conversion data in/out t kqmin t 2 2484 td2 test circuits 1.69k sdo 2484 tc01 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 2484 tc02 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc
ltc2484 13 2484fd applications information converter operation converter operation cycle the ltc2484 is a low power, delta-sigma analog-to-digital converter with an easy to use 4-wire serial interface and automatic differential input current cancellation. its operation is made up of three states. the converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see figure 1). the 4-wire interface consists of serial data output (sdo), serial clock (sck), chip select ( cs ) and serial data input (sdi). initially, the ltc2484 performs a conversion. once the conversion is complete, the device enters the sleep state. convert sleep data output configuration input 2484 f01 true false cs = low and sck figure 1. ltc2484 state transition diagram cs sdo hi-z sig dmy bit 29 msb conversion result bit 28 bit 27 bit 26 lsb24 bit 4 bit 5 bit 3 bit 1 bit 0 bit 2 bit 30 sck sdi sleep data input/output bit 31 eoc en dont care im fob foa spd dont care conversion 2484 f02 sub lsbs figure 2. input/output data timing while in this sleep state, power consumption is reduced by two orders of magnitude. the part re- mains in the sleep state as long as cs is high. the conversion result is held inde? nitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device exits the low power mode and enters the data output state. if cs is pulled high before the ? rst rising edge of sck, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. if cs remains low after the ? rst rising edge of sck, the device begins output- ting the conversion result. taking cs high at this point will terminate the data input and output state and start a new conversion. the conversion result is shifted out of the device through the serial data output pin (sdo) on the falling edge of the serial clock (sck) (see figure 2). the ltc2484 includes a serial data input pin (sdi) in which data is latched by the device on the rising edge of sck (figure 2). the bit stream applied to this pin can be used to select various features of the ltc2484, including an on-chip temperature sensor, line frequency rejection and output data rate. alternatively, this pin may be tied to ground and the part will perform conversions in a default state. in the default state (sdi grounded) the device simply performs conversions on the user applied input with simultaneous rejection of 50hz and 60hz line frequencies.
ltc2484 14 2484fd applications information through timing control of the cs and sck pins, the ltc2484 offers several ? exible modes of operation (internal or external sck and free-running conversion modes). these various modes do not require programming con? guration registers; moreover, they do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. easy drive input current cancellation the ltc2484 combines a high precision delta-sigma adc with an automatic differential input current cancellation front end. a proprietary front-end passive sampling network transparently removes the differential input current. this enables external rc networks and high impedance sensors to directly interface to the ltc2484 without external ampli? ers. the remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see automatic input current cancellation section). this unique architecture does not require on-chip buffers enabling input signals to swing all the way to ground and up to v cc . furthermore, the cancellation does not interfere with the transparent offset and full-scale autocalibration and the absolute accuracy (full-scale + offset + linearity) is maintained with external rc networks. accessing the special features of the ltc2484 the ltc2484 combines a high resolution, low noise ? analog-to-digital converter with an on-chip selectable temperature sensor, programmable digital ? lter and output rate control. these special features are selected through a single 8-bit serial input word during the data input/output cycle (see figure 2). the ltc2484 powers up in a default mode commonly used for most measurements. the device will remain in this mode as long as the serial data input (sdi) is low. in this default mode, the measured input is external, the digital ? lter simultaneously rejects 50hz and 60hz line frequency noise, and the speed mode is 1x (offset automatically, continuously calibrated). a simple serial interface grants access to any or all special functions contained within the ltc2484. in order to change the mode of operation, an enable bit (en) followed by up to 7 bits of data are shifted into the device (see table 1). the ? rst 3 bits, in order to remain pin-compatible with the ltc2480, are dont-cares and can be either high or low. the 4th bit (im) is used to select the internal temperature sensor as the conversion input, while the 5th and 6th bits (fa, fb) combine to determine the line frequency rejection mode. the 7th bit (spd) is used to double the output rate by disabling the offset auto calibration. temperature sensor (im) the ltc2484 includes an on-chip temperature sensor. the temperature sensor is selected by setting im = 1 in the serial input data stream. conversions are performed directly on the temperature sensor by the converter. while operating in this mode, the device behaves as a temperature to bits converter. the digital reading is proportional to the absolute temperature of the device. this feature allows the converter to linearize temperature sensors or continu- ously remove temperature effects from external sensors. table 1. selecting special modes en 2484 tbl1 im foa fob spd comments keep previous mode external input, 50hz and 60hz rejection, autocalibration external input, 50hz rejection, autocalibration external input, 60hz rejection, autocalibration external input, 50hz and 60hz rejection, 2x speed external input, 50hz rejection, 2x speed external input, 60hz rejection, 2x speed temperature input, 50hz and 60hz rejection, autocalibration temperature input, 50hz rejection, autocalibration temperature input, 60hz rejection, autocalibration reserved, do not use 0 1 1 1 1 1 1 1 1 1 1 x 0 0 0 0 0 0 1 1 1 x x 0 0 0 1 1 1 x x x x x 0 1 0 0 1 0 0 1 0 1 x 0 0 1 0 0 1 0 0 1 1
ltc2484 15 2484fd applications information several applications leveraging this feature are presented in more detail in the applications section. while operating in this mode, the speed is set to normal independent of control bit spd. rejection mode (fa, fb) the ltc2484 includes a high accuracy on-chip oscilla- tor with no required external components. coupled with a 4th order digital lowpass ? lter, the ltc2484 rejects line frequency noise. in the default mode, the ltc2484 simultaneously rejects 50hz and 60hz by at least 87db. the ltc2484 can also be con? gured to selectively reject 50hz or 60hz to better than 110db. speed mode (spd) the ltc2484 continuously performs offset calibrations. every conversion cycle, two conversions are automatically performed (default) and the results combined. this result is free from offset and drift. in applications where the offset is not critical, the autocalibration feature can be disabled with the bene? t of twice the output rate. linearity, full-scale accuracy, full-scale drift are identical for both 2x and 1x speed modes. in both the 1x and 2x speed there is no latency. this enables input steps or multiplexer channel changes to settle in a single conver- sion cycle easing system overhead and increasing the effective conversion rate. output data format the ltc2484 serial output data stream is 32 bits long. the ? rst 3 bits represent status information indicating the sign and conversion state. the next 24 bits are the conversion result, msb ? rst. the remaining 5 bits are sub lsbs below the 24-bit level. the third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below Cfs) or an overrange condition (the differential input voltage is above +fs). cs may be pulled high prior to outputting all 32 bits, aborting the data out transfer and initiating a new conversion. bit 31 (? rst output bit) is the end of conversion ( eoc ) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. t h i s b i t i s h i g h d u r i n g t h e c o n v e r s i o n a n d g o e s l o w w h e n the conversion is complete. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indicator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 28 (fourth output bit) is the most signi? cant bit (msb) of the result. this bit in conjunction with bit 29 also provides the underrange or overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 2. table 2. ltc2484 status bits input range bit 31 eoc bit 30 dmy bit 29 sig bit 28 msb v in 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 001/00 C0.5 ? v ref v in < 0v 0001 v in < C0.5 ? v ref 0000 bits 28-5 are the 24-bit conversion result msb ? rst. bits 4C0 are sub lsbs below the 24-bit level. bits 4C0 may be included in averaging or discarded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock (sck) (see figure 2). whenever cs is high, sdo remains high impedance and any externally gener- ated sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must ? rst be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes in real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 31 (eoc) can be captured on the ? rst rising edge of sck. bit 30 is shifted out of the device on the ? rst falling edge of sck. the ? nal data bit (bit 0) is shifted out on the falling edge of the 31st sck and may be latched on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high
ltc2484 16 2484fd applications information indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 31) for the next conversion cycle. table 3 summarizes the output data format. as long as the voltage on the in+ and inC pins is maintained within the C0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital ? lter (commonly implemented as a sinc or comb ? lter). for high resolution, low frequency applications, this ? lter is t y p i c a l l y d e s i g n e d t o r e j e c t l i n e f r e q u e n c i e s o f 5 0 h z o r 6 0 h z plus their harmonics. the ? lter rejection performance is directly related to the accuracy of the converter system clock. the ltc2484 incorporates a highly accurate on-chip oscillator. this eliminates the need for external frequency setting components such as crystals or oscillators. frequency rejection selection (f o ) t h e lt c 24 8 4 i n t e r n a l o s c i l l a t o r p r o v i d e s b e t t e r t h a n 110 d b normal mode rejection at the line frequency and all its harmonics (up to the 255th) for 50hz 2% or 60hz 2%, or better than 87db normal mode rejection from 48hz to 62.4hz. the rejection mode is selected by writing to the on-chip con? guration register and the default mode at por is simultaneous 50hz/60hz rejection. when a fundamental rejection frequency different from 50hz or 60hz is required or when the converter must be synchronized with an outside source, the ltc2484 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the ex ternal signal must be at least 10khz to be detected. the external clock signal duty cycle is not signi? cant as long as the minimum and maximum speci? cations for the high and low periods t heo and t leo are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2484 provides better than 110db normal mode rejection in a frequency range of f eosc /5120 4% and its harmonics. the normal mode rejection as a function of the input frequency deviation from f eosc /5120 is shown in figure 3. whenever an external clock is not present at the f o pin, the converter automatically activates its internal oscilla- tor and enters the internal conversion clock mode. the ltc2484 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses table 3. ltc2484 output data format differential input voltage v in * bit 31 eoc bit 30 dmy bit 29 sig bit 28 msb bit 27 bit 26 bit 25 bit 0 v in * fs** 00110000 fs** C 1lsb 00101111 0.5 ? fs** 00101000 0.5 ? fs** C 1lsb 0 0 1 0 0 1 1 1 0 0 0 1/0*** 0 0 0 0 0 C1lsb 00011111 C0.5 ? fs** 00011000 C0.5 ? fs** C 1lsb 0 0 0 1 0 1 1 1 Cfs** 00010000 v in * < Cfs** 0 0 0 0 1 1 1 1 * the differential input voltage v in = in + C in C . ** the full-scale voltage fs = 0.5 ? v ref . *** the sign bit changes state during the 0 output code when the device is operating in the 2 speed mode .
ltc2484 17 2484fd applications information an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside speci? cations but the following conver- sions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 4 summarizes the duration of each state and the achievable output data rate as a function of f o . ease of use the ltc2484 data output has no latency, ? lter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. the ltc2484 performs offset and full-scale calibrations every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. power-up sequence the ltc2484 automatically enters an internal reset state when the power supply voltage v cc drops below approximately 2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selection. when the v cc voltage rises above this critical threshold, the converter creates an internal power-on reset (por) signal with a duration of approximately 4ms. the por signal clears all internal registers. following the por signal, the ltc2484 starts a normal conversion cycle and follows the succession of states described in figure 1. the table 4. ltc2484 state duration state operating mode duration convert internal oscillator 60hz rejection 133ms, output data rate 7.5 readings/s for 1x speed mode 67ms, output data rate 15 readings/s for 2x speed mode 50hz rejection 160ms, output data rate 6.2 readings/s for 1x speed mode 80ms, output data rate 12.5 readings/s for 2x speed mode 50hz/60hz rejection 147ms, output data rate 6.8 readings/s for 1x speed mode 73.6ms, output data rate 13.6 readings/s for 2x speed mode external oscillator f o = external oscillator with frequency f eosc khz (f eosc /5120 rejection) 41036/f eosc s, output data rate f eosc /41036 readings/s for 1x speed mode 20556/ feosc s, output data rate f eosc /20556 readings/s for 2x speed mode sleep as long as cs = high, after a conversion is complete data output internal serial clock f o = low/high (internal oscillator) as long as cs = low but not longer than 0.83ms (32 sck cycles) f o = external oscillator with frequency f eosc khz as long as cs = low but not longer than 256/f eosc ms (32 sck cycles) external serial clock with frequency f sck khz as long as cs = low but not longer than 32/f sck ms (32 sck cycles) differential input signal frequency deviation from notch frequency f eosc /5120(%) C12 C8 C4 0 4 8 12 normal mode rejection (db) 2484 f03 C80 C85 C90 C95 C100 C105 C110 C115 C120 C125 C130 C135 C140 figure 3. ltc2484 nomal mode rejection when using an external oscillator
ltc2484 18 2484fd applications information ? rst conversion result following por is accurate within the speci? cations of the device if the power supply volt- age is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. on-chip temperature sensor the ltc2484 contains an on-chip ptat (proportional to absolute temperature) signal that can be used as a temperature sensor. the internal ptat has a typical value of 420mv at 27c and is proportional to the abso- lute temperature value with a temperature coef? cient of 420/(27 + 273) = 1.40mv/c (slope), as shown in figure 4. the internal ptat signal is used in a single-ended mode referenced to device ground internally. the 1x speed mode with automatic offset calibration is automatically selected for the internal ptat signal measurement as well. to adjust the slope value. the converter output of the ptat signal, r0 sdo , is measured at a known temperature t0 (in c) and the slope is calculated as: slope = r0 sdo ?v ref t0 + 273 this calibrated slope can be used to calculate the temperature. if the same v ref source is used during calibration and temperature measurement, the actual value of the v ref is not needed to measure the temperature as shown in the calculation below: t c = r sdo ?v ref slope C 273 = r sdo r0 sdo ?t0 + 273 () C 273 reference voltage range the ltc2484 external reference voltage range is 0.1v to v cc . the converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. a reduced reference voltage will improve the converter performance when operated with an external conversion clock (external f o signal) at substantially higher output data rates (see the output data rate section). v ref must be 1.1v to use the internal temperature sensor. the negative reference input to the converter is internally tied to gnd. gnd (pin 8) should be connected to a ground plane through as short a trace as possible to minimize voltage drop. the ltc2484 has an average operational current of 160a and for 0.1 parasitic resistance, the voltage drop of 16v causes a gain error of 3.2ppm for v ref = 5v. input voltage range the analog input is truly differential with an absolute/com- mon mode range for the in + and in C input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2484 converts the bipolar differential input signal, temperature (c) C60 v ptat (mv) 500 600 120 2484 f04 400 200 30 090 C30 60 300 v cc = 5v im = 1 f o = gnd slope = 1.40mv/c figure 4. internal ptat signal vs temperature when using the internal temperature sensor, if the output code is nor malized to r sdo = v ptat /v ref , the temperature is calculated using the following formula: t k = r sdo ?v ref slope in kelvin and t c = r sdo ?v ref slope C273 in c where slope is nominally 1.4mv/c since the ptat signal can have an initial value variation which results in errors in slope, to achieve better tem- perature measurements, a one-time calibration is needed
ltc2484 19 2484fd applications information v in = in + C in C , from Cfs to +fs where fs = 0.5 ? v ref . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. since the differential input current cancellation does not rely on an on-chip buffer, current cancellation as well as dc performance is maintained rail-to-rail. input signals applied to in + and in C pins may extend by 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the in + and in C pins without affecting the performance of the devices. the effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the input current/reference current sections. in addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. serial interface timing modes the ltc2484s 4-wire interface is spi and microwire compatible. this interface offers several ? exible modes of operation. these include internal/external serial clock, 3 - o r 4 - w i r e i / o, s i n g l e c y c l e o r c o n t i n u o u s c o n v e r s i o n . t h e following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low or f o = high) or an external oscillator connected to the f o pin. refer to table 5 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle (see figure 5). t he s er i al clock mode is s ele c ted on the f alling edge of cs . to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. independent of cs , the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state, its conversion result i s h e l d i n a n i n t e r n a l s t a t i c s h i f t r e g i s t e r. t h e d e v i c e r e m a i n s in the sleep state until the ? rst rising edge of sck is seen while cs is low. the input data is then shifted in via the sdi pin on the rising edge of sck (including the ? rst rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the ? rst rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion. sdo goes high ( eoc = 1) indicating a conversion is in progress. table 5. ltc2484 interface timing modes configuration sck source conversion cycle control data output control connection and waveforms external sck, single cycle conversion external cs and sck cs and sck figures 5, 6 external sck, 3-wire i/o external sck sck figure 7 internal sck, single cycle conversion internal cs cs figures 8, 9 internal sck, 3-wire i/o, continuous conversion internal continuous internal figure 10
ltc2484 20 2484fd applications information en dont care im foa fob spd sdi dont care dont care sdo sck (external) cs data output conversion sleep sleep sleep test eoc data output hi-z hi-z hi-z conversion 2484 f06 msb sig bit 8 bit 27 bit 26 bit 25 bit 24 bit 9 bit 28 bit 29 bit 30 eoc bit 31 bit 0 eoc hi-z test eoc test eoc (optional) v cc f o v ref in + in C sck sdi sdo cs gnd 210 int/ext clock 3 4 5 9 7 8 6 1 reference voltage 0.1v to v cc analog input 1f 2.7v to 5.5v ltc2484 4-wire spi interface figure 6. external serial clock, reduced data output length eoc bit 31 sdo sck (external) cs en dont care im foa fob spd sdi dont care test eoc msb sig bit 0 lsb bit 5 bit 27 bit 26 bit 25 bit 24 bit 28 bit 29 bit 30 sleep sleep data output conversion 2484 f05 conversion hi-z hi-z hi-z test eoc v cc f o v ref in + in C sck sdi sdo cs gnd 210 int/ext clock 3 4 5 9 7 8 6 1 reference voltage 0.1v to v cc analog input 1f 2.7v to 5.5v ltc2484 4-wire spi interface dont care test eoc (optional) figure 5. external serial clock, single cycle operation
ltc2484 21 2484fd applications information at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pull- ing cs high anytime between the ? rst rising edge and the 32nd falling edge of sck (see figure 6). on the rising edge of cs , the device aborts the data output state and immediately initiates a new conversion. if the device has not ? nished loading the last input bit spd of sdi by the time cs is pulled high, the sdi information is discarded and the previous con? guration is kept. this is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. external serial clock, 3-wire i/o this timing mode utilizes a 3-wire serial i/o interface. the conversion result is shifted out of the device by an externally generated serial clock (sck) signal (see figure 7). cs may be permanently tied to ground, simplifying the user interface or transmission over an isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is con- cluded typically 4ms after v cc exceeds approximately 2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. since cs is tied low, the end-of-conversion ( eoc ) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion ends. on the falling edge of eoc , the conversion result is loaded into an internal static shift register. the input data is then shifted in via the sdi pin on the rising edge of sck (including the ? rst rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck. eoc can be latched on the ? rst rising edge of sck. on the 32nd falling edge of sck, sdo goes high ( eoc = 1) indicating a new conversion has begun. en gs2 gs1 gs0 im fa fb spd sdi* dont care dont care eoc bit 23 sdo sck (external) cs msb sig bit 0 im lsb bit 4 bit 19 bit 18 bit 17 bit 16 bit 20 bit 21 bit 22 data output conversion 2484 f07 conversion v cc f o v ref in + in C sck sdi sdo cs gnd 210 int/ext clock 3 4 5 9 7 8 6 1 reference voltage 0.1v to v cc analog input 1f 2.7v to 5.5v ltc2484 3-wire spi interface figure 7. external serial clock, cs = 0 operation
ltc2484 22 2484fd applications information internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle (see figure 8). in order to select the internal serial clock timing mode, the serial clock pin (sck) must be ? oating (hi-z) or pulled high prior to the falling edge of cs . the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs . an internal weak pull-up resis- tor is active on the sck pin during the falling edge of cs ; therefore, the internal serial clock timing mode is automati- cally selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. when testing eoc , if the conversion is complete ( eoc = 0), the device will exit the low power mode during the eoc test. in order to allow the device to return to the low power sleep state, cs must be pulled high before the ? rst rising edge of sck. in the internal sck timing mode, sck goes h i g h a n d t h e d e v i c e b e g i n s o u t p u t t i n g d a t a a t t i m e t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc ). the value of t eoctest is 12s if the device is using its internal oscillator. if f o is driven by an external oscillator of frequency f eosc , then t eoctest is 3.6/f eosc in seconds. if cs is pulled high before time t eoctest , the device returns to the sleep state and the conversion result is held in the internal static shift register. if cs remains low longer than t eoctest , the ? rst rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data i/o cycle concludes after the 32nd rising edge. the input data is shifted in via the sdi pin on the rising edge of sck (including the ? rst rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the ? rst rising edge of sck and the last bit of the conversion result on the 32nd rising edge of sck. after the 32nd rising edge, sdo goes high ( eoc = 1), sck stays high and a new conversion starts. cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the ? rst and 32nd rising edge of sck (see figure 9). on the rising edge of cs , the device aborts the data output state and immediately initiates a new conver- sion. if the device has not ? nished loading the last input bit (spd) of sdi by the time cs is pulled high, the sdi information is discarded and the previous con? guration is still kept. this is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. if cs is pulled high while the converter is driving sck low, the internal pull-up is not available to restore sck to a logic high state. this will cause the device to exit the internal serial clock mode on the next falling edge of cs . this can be avoided by adding an external 10k pull-up resistor to the sck pin or by never pulling cs high when sck is low. whenever sck is low, the ltc2484s internal pull-up at pin sck is disabled. normally, sck is not externally driven if the device is in the internal sck timing mode. however, certain applications may require an external driver on sck. if this driver goes hi-z after outputting a low signal, the ltc2484s internal pull-up remains disabled. hence, sck remains low. on the next falling edge of cs , the device is switched to the external sck timing mode. by adding an external 10k pull-up resistor to sck, this pin goes high once the external driver goes hi-z. on the next cs falling edge, the device will remain in the internal sck timing mode. a similar situation may occur during the sleep state when cs is pulsed high-low-high in order to test the conver- sion status. if the device is in the sleep state ( eoc = 0), sck will go low. once cs goes high (within the time period de? ned above as t eoctest ), the internal pull-up is activated. for a heavy capacitive load on the sck pin, the internal pull-up may not be adequate to return sck to a high level before cs goes low again. this is not a concern under normal conditions where cs remains low after detecting eoc = 0. this situation is easily overcome by adding an external 10k pull-up resistor to the sck pin.
ltc2484 23 2484fd applications information en dont care im foa fob spd sdi dont care dont care sdo sck (internal) cs >t eoctest msb sig bit 8 test eoc (optional) test eoc bit 27 bit 26 bit 25 bit 24 bit 28 bit 29 bit 30 eoc bit 31 eoc bit 0 sleep sleep data output hi-z hi-z hi-z hi-z hi-z data output conversion conversion sleep 2484 f09 ltc2484 24 2484fd applications information internal serial clock, 3-wire i/o, continuous conversion this timing mode uses a 3-wire interface. the conversion result is shifted out of the device by an internally gener- ated serial clock (sck) signal, see figure 10. cs may be permanently tied to ground, simplifying the user interface or transmission over an isolation barrier. the internal serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 1ms after v cc exceeds 2v. an internal weak pull-up is active during the por cycle; therefore, the internal serial clock timing mode is automatically selected if sck is not externally driven low (if sck is loaded such that the internal pull-up cannot pull the pin high, the external sck mode will be selected). during the conversion, the sck and the serial data output pin (sdo) are high ( eoc = 1). once the conversion is complete, sck and sdo go low ( eoc = 0) indicating the conversion has ? nished and the device has entered the low power sleep state. the part remains in the sleep state a minimum amount of time (1/2 the internal sck period) then immediately begins outputting data. the data input/output cycle begins on the ? rst rising edge of sck and ends after the 32nd rising edge. the input data is then shifted in via the sdi pin on the rising edge of sck (including the ? rst rising edge) and the output data is shifted out of the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shif t the conversion result into external circuitry. eoc can be latched on the ? rst ris- ing edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. after the 32nd rising edge, sdo goes high ( eoc = 1) indicating a new conversion is in progress. sck remains high during the conversion. en gs2 gs1 gs0 im fa fb spd sdi* dont care dont care sdo sck (internal) cs lsb msb sig bit 4 bit 0 im bit 19 bit 18 bit 17 bit 16 bit 20 bit 21 bit 22 eoc bit 23 data output conversion conversion 2484 f10 v cc f o v ref in + in C sck sdi sdo cs gnd 210 int/ext clock 3 4 5 9 7 8 6 1 reference voltage 0.1v to v cc analog input 1f 2.7v to 5.5v ltc2484 3-wire spi interface 10k v cc figure 10. internal serial clock, cs = 0 continuous operation
ltc2484 25 2484fd applications information preserving the converter accuracy the ltc2484 is designed to reduce as much as possible the conversion result sensitivity to device decoupling, pcb layout, antialiasing circuits, line frequency perturbations and so on. nevertheless, in order to preserve the 24-bit accuracy capability of this part, some simple precautions are required. digital signal levels the ltc2484s digital interface is easy to use. its digital inputs (sdi, f o , cs and sck in external sck mode of operation) accept standard cmos logic levels and the internal hysteresis receivers can tolerate edge transition times as slow as 100s. however, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. the digital output signals (sdo and sck in internal sck mode of operation) are less of a concern because they are not generally active during the conversion state. while a digital input signal is in the range 0.5v to (v cc C 0.5v), the cmos input receiver draws additional current from the power supply. it should be noted that, when any one of the digital input signals (sdi, f o , cs and sck in external sck mode of operation) is within this range, the power supply current may increase even if the signal in question is at a valid logic level. for micropower operation, it is recommended to drive all digital input signals to full cmos levels [v il < 0.4v and v oh > (v cc C 0.4v)]. during the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the pins can severely disturb the analog to digital conversion process. undershoot and overshoot occur because of the imped- ance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to the ltc2484. for reference, on a regular fr-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. thus, a driver gen- erating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. this problem becomes particularly dif? cult when shared control lines are used and multiple re? ections may occur. the solution is to carefully terminate all transmission lines close to their characteristic impedance. parallel termination near the ltc2484 pin will eliminate this problem but will increase the driver power dissipa- tion. a series resistor between 27 and 56 placed near the driver output pin will also eliminate this problem without additional power dissipation. the actual resistor value depends upon the trace impedance and connection topology. a n a l t e r n a t e s o l u t i o n i s t o r e d u c e t h e e d g e r a t e o f t h e c o n t r o l signals. it should be noted that using ver y slow edges will increase the converter power supply current during the transition time. the differential input architecture reduces the converters sensitivity to ground currents. particular attention must be given to the connection of the f o signal when the ltc2484 is used with an external conversion clock. this clock is active during the conver- sion time and the normal mode rejection provided by the internal digital ? lter is not very high at this frequency. a normal mode signal of this frequency at the converter reference terminals can result in dc gain and inl errors. a normal mode signal of this frequency at the converter input terminals can result in a dc offset error. such pertur- bations can occur due to asymmetric capacitive coupling between the f o signal trace and the converter input and/or reference connection traces. an immediate solution is to maintain maximum possible separation between the f o signal trace and the input/reference signals. when the f o signal is parallel terminated near the converter, substantial ac current is ? owing in the loop formed by the f o con- nection trace, the termination and the ground return path. thus, perturbation signals may be inductively coupled into the converter input and/or reference. in this situation, the user must reduce to a minimum the loop area for the f o signal as well as the loop area for the differential input and reference connections. even when f o is not driven, other nearby signals pose similar emi threats which will be minimized by following good layout practices.
ltc2484 26 2484fd applications information driving the input and reference the input and reference pins of the ltc2484 converter are directly connected to a network of sampling capaci- tors. depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transfer- ring small amounts of charge in the process. a simpli? ed equivalent circuit is shown in figure 11. for a simple approximation, the source impedance r s driving an analog input pin (in + , in C , v ref + or gnd) can be considered to form, together with r sw and c eq (see figure 11), a ? rst order passive network with a time constant = (r s + r sw ) ? c eq . the converter is able to sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant, . the sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worst-case circumstances, the errors may add. when using the internal oscillator, the ltc2484s front-end switched-capacitor network is clocked at 123khz corre- sponding to an 8.1s sampling period. thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that 8.1s/14 = 580ns. when an external oscillator of frequency f eosc is used, the sampling period is 2.5/f eosc and, for a settling error of less than 1ppm, 0.178/f eosc . automatic differential input current cancellation in applications where the sensor output impedance is low (up to 10k with no external bypass capacitor or up to 500 with 0.001f bypass), complete settling of the input occurs. in this case, no errors are introduced and direct digitization of the sensor is possible. for many applications, the sensor output impedance combined with external bypass capacitors produces rc time constants much greater than the 580ns required for 1ppm accuracy. for example, a 10k bridge driving a 0.1f bypass capacitor has a time constant an order of magnitude greater than the required maximum. historically, settling issues were solved using buffers. these buffers led to increased noise, reduced dc performance (offset/ drift), limited input/output swing (cannot digitize signals near ground or v cc ), added system cost and increased power. the ltc2484 uses a proprietary switching algo- v ref + v in + v cc r sw (typ) 10k i leak i leak v cc i leak i leak v cc r sw (typ) 10k c eq 12pf (typ) r sw (typ) 10k i leak i in + v in C i in C i ref + i ref C 2484 f11 i leak v cc i leak i leak switching frequency f sw = 123khz internal oscillator f sw = 0.4 ? f eosc external oscillator gnd r sw (typ) 10k figure 11. ltc2484 equivalent analog input circuit
ltc2484 27 2484fd applications information rithm that forces the average differential input current to zero independent of external settling errors. this allows accurate direct digitization of high impedance sensors without the need for buffers. additional errors resulting from mismatched leakage currents must also be taken into account. the switching algorithm forces the average input current on the positive input (i in + ) to be equal to the average input current on the negative input (i in C ). over the complete conversion cycle, the average differential input current (i in + C i in C ) is zero. while the differential input current is zero, the common mode input current (i in + + i in C )/2 is proportional to the difference between the common mode input voltage (v incm ) and the common mode reference voltage (v refcm ). in applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balance bridge type application, both the differential and common mode input current are zero. the accuracy of the converter is unaffected by settling errors. mismatches in source impedances between in + and in C also do not affect the accuracy. in applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between v incm and v refcm . for a reference common mode of 2.5v and an input common mode of 1.5v, the common mode input current is approximately 0.74a (in simultaneous 50hz/60hz rejection mode). this common mode input current has no effect on the accuracy if the external source impedances tied to in + and in C are matched. mismatches in these source impedances lead to a ? xed offset error but do not affect the linearity or full- scale reading. a 1% mismatch in 1k source resistances leads to a 15ppm shift (74v) in offset voltage. in applications where the common mode input voltage varies as a function of input signal level (single-ended input, rtds, half bridges, current sensors, etc.), the common mode input current varies proportionally with input voltage. for the case of balanced input impedances, the common mode input current effects are rejected by the large cmrr of the ltc2484 leading to little degrada- tion in accuracy. mismatches in source impedances lead to gain errors proportional to the difference between the common mode input voltage and the common mode ref- erence volt age. 1% mismatches in 1k source resist ances l e a d t o g a i n w o r s t- c a s e g a i n e r r o r s o n t h e o r d e r o f 15 p p m (for 1v differences in reference and input common mode voltage). table 6 summarizes the effects of mismatched source impedance and differences in reference/input common mode voltages. table 6. suggested input con? guration for ltc2484 balanced input resistances unbalanced input resistances constant v in(cm) C v ref(cm) c in > 1nf at both in + and in C . can take large source resistance with negligible error c in > 1nf at both in + and in C . can take large source resistance. unbalanced resistance results in an offset which can be calibrated varying v in(cm) C v ref(cm) c in > 1nf at both in + and in C . can take large source resistance with negligible error minimize in + and in C capacitors and avoid large source impedance (<5k recommended) the magnitude of the dynamic input current depends upon t h e s i z e o f t h e v e r y s t a b l e i n t e r n a l s a m p l i n g c a p a c i t o r s a n d upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. such a speci? cation can also be easily achieved by an external clock. when relatively stable resistors (50ppm/c) are used for the external source impedance seen by in + and in C , the expected drift of the dynamic current and offset will be insigni? cant (about 1% of their respective values over the entire temperature and voltage range). even for the most stringent applications, a one-time calibration operation may be suf? cient. in addition to the input sampling charge, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na (10na max), results in a small offset shift. a 1k source resistance will create a 1v typical and 10v maximum offset voltage.
ltc2484 28 2484fd applications information reference current in a similar fashion, the ltc2484 samples the differential reference pins v ref + and gnd transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. this current does not change the converter offset, but it may degrade the gain and inl performance. the effect of this current can be analyzed in two distinct situations. for relatively small values of the external reference capaci- tors (c ref < 1nf), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c ref will deteriorate the converter offset and gain performance without signi? cant bene? ts of reference ? ltering and the user is advised to avoid them. larger values of reference capacitors (c ref > 1nf) may be required as reference ? lters in certain con? gurations. such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. in the following discussion, it is assumed the input and reference common mode are the same. using internal oscillator for 60hz mode, the typical differential reference resistance is 1m which generates a full-scale (v ref /2) gain error of 0.51ppm for each ohm of source resistance driving the v ref pin. for 50hz/60hz mode, the related difference resistance is 1.1m and the resulting full-scale error is 0.46ppm for each ohm of source resistance driving the v ref pin. for 50hz mode, the related difference resistance is 1.2m and the resulting full-scale error is 0.42ppm for each ohm of source resistance driving the v ref pin. when f o is driven by an external oscillator with a frequency f eosc (external conversion clock operation), the typical differen- tial reference resistance is 0.30 ? 10 12 /f eosc and each ohm of source resistance driving the v ref pin will result c in 2484 f12 v incm + 0.5v in r source in + ltc2484 c par 20pf c in v incm C 0.5v in r source in C c par 20pf figure 12. an rc network at in + and in C r source () 1 +fs error (ppm) C20 0 20 1k 100k 2484 f13 C40 C60 C80 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c in = 0pf c in = 100pf c in = 1nf, 0.1f, 1f figure 13. +fs error vs r source at in + or in C r source () 1 Cfs error (ppm) C20 0 20 1k 100k 2484 f14 C40 C60 C80 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c in = 0pf c in = 100pf c in = 1nf, 0.1f, 1f figure 14. Cfs error vs r source at in + or in C
ltc2484 29 2484fd applications information in 1.67 ? 10 C6 ? f eosc ppm gain error. the typical +fs and Cfs errors for various combinations of source resistance seen by the v ref pin and external capacitance connected to that pin are shown in figures 15-18. in addition to this gain error, the converter inl per- formance is degraded by the reference source imped- ance. the inl is caused by the input dependent terms Cv in 2 /(v ref ? r eq ) C (0.5 ? v ref ? d t )/r eq in the reference pin current as expressed in figure 11. when using internal oscillator and 60hz mode, every 100 of reference source resistance translates into about 0.67ppm additional inl error. when using internal oscillator and 50hz/60hz mode, every 100 of reference source resistance translates into about 0.61ppm additional inl error. when using internal oscillator and 50hz mode, every 100 of reference source resistance translates into about 0.56ppm additional inl error. when f o is driven by an external oscillator with a frequency f eosc , every 100 of source resistance driving r source () 0 +fs error (ppm) 50 70 90 10k 2484 f15 30 10 40 60 80 20 0 C10 10 100 1k 100k v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf figure 15. +fs error vs r source at v ref (small c ref ) r source () 0 Cfs error (ppm) C30 C10 10 10k 2484 f16 C50 C70 C40 C20 0 C60 C80 C90 10 100 1k 100k v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf figure 16. Cfs error vs r source at v ref (small c ref ) r source () 0 +fs error (ppm) 300 400 500 800 2484 f17 200 100 0 200 400 600 1000 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c ref = 1f, 10f c ref = 0.1f c ref = 0.01f figure 17. +fs error vs r source at v ref (large c ref ) figure 18. Cfs error vs r source at v ref (large c ref ) r source () 0 Cfs error (ppm) C200 C100 0 800 2484 f18 C300 C400 C500 200 400 600 1000 v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c ref = 1f, 10f c ref = 0.1f c ref = 0.01f
ltc2484 30 2484fd applications information v ref translates into about 2.18 ? 10 C6 ? f eosc ppm addi- tional inl error. figure 19 shows the typical inl error due to the source resistance driving the v ref pin when large c ref values are used. the user is advised to minimize the source impedance driving the v ref pin. entire temperature and voltage range). even for the most stringent applications a one-time calibration operation may be suf? cient. in addition to the reference sampling charge, the refer- ence pins esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na (10na max), results in a small gain error. a 100 source resistance will create a 0.05v typical and 0.5v maximum full-scale error. output data rate when using its internal oscillator, the ltc2484 produces up to 7.5 samples per second (sps) with a notch frequency of 60hz, 6.25sps with a notch frequency of 50hz and 6.8sps with the 50hz/60hz rejection mode. the actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insigni? cantly short. when oper- ated with an external conversion clock (f o connected to an external oscillator), the ltc2484 output data rate can be increased as desired. the duration of the conversion phase is 41036/f eosc . if f eosc = 307.2khz, the converter behaves as if the internal oscillator is used and the notch is set at 60hz. an increase in f eosc over the nominal 307.2khz will trans- late into a proportional increase in the maximum output data rate. the increase in output rate is nevertheless accompanied by three potential effects, which must be carefully considered. fir st, a change in f eosc will result in a propor tional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. in many applications, the subsequent per- formance degradation can be substantially reduced by relying upon the ltc2484s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. the user should avoid single-ended input ? lters and should maintain a very high degree of matching and symmetry in the circuits driving the in + and in C pins. second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred figure 19. inl vs differential input voltage and reference source resistance for c ref > 1f v in /v ref (v) C0.5 inl (ppm of v ref ) 2 6 10 0.3 2484 f19 C2 C6 0 4 8 C4 C8 C10 C0.3 C0.1 0.1 0.5 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c c ref = 10f r = 1k r = 100 r = 500 in applications where the reference and input common mode voltages are different, extra errors are introduced. for every 1v of the reference and input common mode voltage difference (v refcm C v incm ) and a 5v reference, each ohm of reference source resistance introduces an extra (v refcm C v incm )/(v ref ? r eq ) full-scale gain error, which is 0.074ppm when using internal oscillator and 60hz mode. when using internal oscillator and 50hz/60hz mode, the extra full-scale gain error is 0.067ppm. when using internal oscillator and 50hz mode, the extra gain error is 0.061ppm. if an external clock is used, the corresponding extra gain error is 0.24 ? 10 C6 ? f eosc ppm. the magnitude of the dynamic reference current depends u p o n t h e s i z e o f t h e v e r y s t a b l e i n t e r n a l s a m p l i n g c a p a c i t o r s and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. such a speci? cation can also be easily achieved by an external clock. when relatively stable resistors (50ppm/c) are used for the external source impedance seen by v ref + and gnd, the expected drift of the dynamic current gain error will be insigni? cant (about 1% of its value over the
ltc2484 31 2484fd applications information through the input and the reference pins. if large external input and/or reference capacitors (c in , c ref ) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter perfor- mance for any value of f eosc . if small external input and/ or reference capacitors (c in , c ref ) are used, the effect of the external source resistance upon the ltc2484 typical performance can be inferred from figures 13, 14, 15 and 16 in which the horizontal axis is scaled by 307200/f eosc . third, an increase in the frequency of the external oscillator above 1mhz (a more than 3 increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. this will result in a progressive degradation in the converter accuracy and linearity. typical measured performance curves for output data rates up to 100 readings per second are shown in figures 20 to 27. in order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per output data rate (readings/sec) C10 offset error (ppm of v ref ) 10 30 50 0 20 40 20 40 60 80 2484 f20 100 10 030507090 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock t a = 85c t a = 25c figure 20. offset error vs output data rate and temperature output data rate (readings/sec) 0 0 +fs error (ppm of v ref ) 500 1500 2000 2500 3500 10 50 70 2484 f21 1000 3000 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c figure 21. +fs error vs output data rate and temperature figure 22. Cfs error vs output data rate and temperature output data rate (readings/sec) 0 C3500 Cfs error (ppm of v ref ) C3000 C2000 C1500 C1000 0 10 50 70 2484 f22 C2500 C500 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 20 24 10 50 70 2484 f23 14 22 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock res = log 2 (v ref /noise rms ) t a = 85c t a = 25c figure 23. resolution (noise rms 1lsb) vs output data rate and temperature
ltc2484 32 2484fd applications information second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. in certain circumstances, a reduction of the differential reference voltage may be bene? cial. input bandwidth the combined effect of the internal sinc 4 digital ? lter and of the analog and digital autocalibration circuits determines the ltc2484 input bandwidth. when the internal oscillator output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 50 70 2484 f24 14 20 40 90 100 20 30 60 80 t a = 85c t a = 25c v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock res = log 2 (v ref /inl max ) figure 24. resolution (inl rms 1lsb) vs output data rate and temperature output data rate (readings/sec) 0 C10 offset error (ppm of v ref ) C5 5 10 20 10 50 70 2484 f25 0 15 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c figure 25. offset error vs output data rate and reference voltage figure 26. resolution (noise rms 1lsb) vs output data rate and reference voltage figure 27. resolution (inl rms 1lsb) vs output data rate and reference voltage output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 20 24 10 50 70 2484 f26 14 22 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c res = log 2 (v ref /noise rms ) v cc = 5v, v ref = 2.5v v cc = v ref = 5v output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 50 70 2484 f27 14 20 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v ref C = gnd f o = ext clock t a = 25c res = log 2 (v ref /inl max ) is used with the notch set at 60hz, the 3db input bandwidth is 3.63hz. when the internal oscillator is used with the notch set at 50hz, the 3db input bandwidth is 3.02hz. if an external conversion clock generator of frequency f eosc is connected to the f o pin, the 3db input bandwidth is 11.8 ? 10 C6 ? f eosc . due to the complex ? ltering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a ? rst order ? lter with the pole located
ltc2484 33 2484fd applications information at the 3db frequency. when the internal oscillator is used, the shape of the ltc2484 input bandwidth is shown in figure 28. when an external oscillator of frequency f eosc is used, the shape of the ltc2484 input bandwidth can be derived from figure 28, 60hz mode curve in which the horizontal axis is scaled by f eosc /307200. the conversion noise (600nv rms typical for v ref = 5v) can be modeled by a white noise source connected to a noise free converter. the noise spectral density is 47nv hz for an infinite bandwidth source and 64nv hz for a single 0.5mhz pole source. from these numbers, it is clear that particular attention must be given to the design of external amplification circuits. such circuits face the simultaneous requirements of very low bandwidth (just a few hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500khz) necessary to drive the input switched- capacitor network. a possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. when external ampli? ers are driving the ltc2484, the adc input referred system noise calculation can be simpli? ed by figure 29. the noise of an ampli? er driving the ltc2484 input pin can be modeled as a band limited white noise source. its bandwidth can be approximated by the bandwidth of a single pole lowpass ? lter with a corner frequency f i . the ampli? er noise spectral density is n i . from figure 29, using f i as the x-axis selector, we can ? nd on the y-axis the noise equivalent bandwidth freq i of the input driving ampli? er. this bandwidth includes the band limiting effects of the adc internal calibration and ? ltering. the noise of the driving ampli? er referred to the converter input and including all these effects can be calculated as n = n i ? freq i . the total system noise (referred to the ltc2484 input) can now be obtained by summing as square root of sum of squares the three adc input referred noise sources: the ltc2484 internal noise, the noise of the in + driving ampli? er and the noise of the in C driving ampli? er. if the f o pin is driven by an ex ternal oscillator of frequency f eosc , figure 29 can still be used for noise calculation if the x-axis is scaled by f eosc /307200. for large values of the ratio f eosc / 3 0 7 2 0 0, t h e f i gur e 2 9 p l o t a c c ur a c y b e g i n s to decrease, but at the same time the ltc2484 noise ? oor rises and the noise contribution of the driving ampli? ers lose signi? cance. differential input signal frequency (hz) 0 input signal attenuation (db) C3 C2 C1 0 4 2484 f28 C4 C5 C6 1 2 3 5 50hz mode 60hz mode 50hz and 60hz mode figure 28. input signal bandwidth using the internal oscillator input noise source single pole equivalent bandwidth (hz) 1 input referred noise equivalent bandwidth (hz) 10 0.1 1 10 100 1k 10k 100k 1m 2484 f29 0.1 100 50hz mode 60hz mode figure 29. input referred noise equivalent bandwidth of an input connected white noise source
ltc2484 34 2484fd applications information normal mode rejection and antialiasing one of the advantages delta-sigma adcs offer over conventional adcs is on-chip digital ? ltering. combined with a large oversampling ratio, the ltc2484 signi? cantly simpli? es antialiasing ? lter requirements. additionally, the input current cancellation feature of the ltc2484 al- lows external lowpass ? ltering without degrading the dc performance of the device. the sinc 4 digital ? lter provides greater than 120db normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ). the ltc2484s autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal ? ltering both in the analog and digital domain. independent of the operating mode, f s = 256 ? f n = 2048 ? f out(max) where f n is the notch frequency and f out(max) is the maximum output data rate. in the internal oscilla- tor mode with a 50hz notch setting, f s = 12800hz, with 50hz/60hz rejection, f s = 13960hz and with a 60hz notch setting f s = 15360hz. in the external oscillator mode, f s = f eosc /20. the performance of the normal mode rejection is shown in figures 30 and 31. in 1x speed mode, the regions of low rejection occurring at integer multiples of f s have a very narrow bandwidth. magni? ed details of the normal mode rejection curves are shown in figure 32 (rejection near dc) and figure 33 (rejection at f s = 256f n ) where f n represents the notch frequency. these curves have been derived for the exter- nal oscillator mode but they can be used in all operating modes by appropriately selecting the f n value. the user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by figures 34, 35 and 36. typical measured values of the normal mode rejection of the ltc2484 operating with an internal oscillator and a 60hz notch setting are shown in figure 34 superimposed over the theoretical calculated curve. similarly, the measured normal mode rejection of the ltc2484 for the 50hz rejection mode and 50hz/60hz rejection mode are shown in figures 35 and 36. as a result of these remarkable normal mode speci? ca- tions, minimal (if any) antialias ? ltering is required in front of the ltc2484. if passive rc components are placed in front of the ltc2484, the input dynamic current should differential input signal frequency (hz) 0f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s 11f s 12f s input normal mode rejection (db) 2484 f30 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 differential input signal frequency (hz) 0f s input normal mode rejection (db) 2484 f31 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s figure 30. input normal mode rejection, internal oscillator and 50hz notch mode figure 31. input normal mode rejection, internal oscillator and 60hz notch mode of external oscillator
ltc2484 35 2484fd applications information input signal frequency (hz) input normal mode rejection (db) 2484 f32 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2484 f33 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 figure 32. input normal mode rejection at dc figure 33. input normal mode rejection at f s = 256f n input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2484 f34 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data figure 34. input normal mode rejection vs input frequency with input perturbation of 100% full-scale (60hz notch) input frequency (hz) 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 normal mode rejection (db) 2484 f35 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25 c measured data calculated data figure 35. input normal mode rejection vs input frequency with input perturbation of 100% full-scale (50hz notch) figure 36. input normal mode rejection vs input frequency with input perturbation of 100% full-scale (50hz/60hz mode) input frequency (hz) 0 20 40 60 80 100 120 140 160 180 200 220 normal mode rejection (db) 2484 f36 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data
ltc2484 36 2484fd applications information be considered (see input current section). in this case, the differential input current cancellation feature of the ltc2484 allows external rc networks without signi? cant degradation in dc performance. traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. the proprietary architecture used for the ltc2484 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full-scale. in many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and the ltc2484 is eminently suited for such tasks. when the perturbation is differential, the speci? cation of interest is the normal mode rejection for large input signal levels. with a reference voltage v ref = 5v, the ltc2484 has a full-scale differential input range of 5v peak-to-peak. figures 37 and 38 show measurement results for the ltc2484 normal mode rejection ratio with a 7.5v peak-to-peak (150% of full-scale) input signal superimposed over the more tradi- tional normal mode rejection ratio results obtained with a 5v peak-to-peak (full-scale) input signal. in figure 37, the ltc2484 uses the internal oscillator with the notch set at 60hz (f o = low) and in figure 38 it uses the internal oscillator with the notch set at 50hz. it is clear that the ltc2484 rejection performance is maintained with no compromises in this extreme situation. when operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings. input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2484 f37 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v incm = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) input frequency (hz) 0 normal mode rejection (db) 2484 f38 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 figure 37. measured input normal mode rejection vs input freq- uency with input perturbation of 150% full-scale (60hz notch) figure 38. measured input normal mode rejection vs input freq- uency with input perturbation of 150% full-scale (50hz notch)
ltc2484 37 2484fd applications information input signal frequency (f n ) input normal rejection (db) 2484 f39 0 C20 C40 C60 C80 C100 C120 0 f n 2f n 3f n 4f n 5f n 6f n 7f n 8f n input signal frequency (f n ) input normal rejection (db) 2484 f4 0 0 C20 C40 C60 C80 C100 C120 250 248 252 254 256 258 260 262 264 figure 39. input normal mode rejection 2x speed mode figure 40. input normal mode rejection 2x speed mode input frequency (hz) 0 normal mode rejection (db) 50 100 125 225 25 75 150 175 200 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v incm = 2.5v v in(p-p) = 5v f o = gnd t a = 25c measured data calculated data figure 41. input normal mode rejection vs input frequency, 2x speed mode and 50hz/60hz mode differential input signal frequency (hz) 48 C70 C80 C90 C100 C110 C120 C130 C140 54 58 50 52 56 60 62 normal mode rejection (db) no average with running average figure 42. input normal mode rejection 2x speed mode using the 2x speed mode of the ltc2484, the device bypasses the digital offset calibration operation to double the output data rate. the superior normal mode rejection is maintained as shown in figures 30 and 31. however, the magni? ed details near dc and f s = 256f n are different, see figures 39 and 40. in 2x speed mode, the bandwidth is 11.4hz for the 50hz rejection mode, 13.6hz for the 60hz rejection mode and 12.4hz for the 50hz/60hz rejection mode. typical measured values of the normal mode rejec- tion of the ltc2484 operating with the internal oscillator and 2x speed mode is shown in figure 41. when the ltc2484 is con? gured in 2x speed mode, by performing a running average, a sinc 1 notch is combined with the sinc 4 digital ? lter, yielding the normal mode rejection identical as that for the 1x speed mode. the averaging operation still keeps the output rate with the following algorithm: result 1 = average (sample 0, sample 1) result 2 = average (sample 1, sample 2) result n = average (sample n C 1, sample n) the main advantage of the running average is that it achieves simultaneous 50hz/60hz rejection at twice the effective output rate, as shown in figure 42. the raw output data provides a better than 70db rejection over 48hz to 62.4hz, which covers both 50hz 2% and 60hz 2%. with running average on, the rejection is better than 87db for both 50hz 2% and 60hz 2%.
ltc2484 38 2484fd applications information complete thermocouple measurement system with cold junction compensation the ltc2484 is ideal for direct digitization of thermocouples and other low voltage output sensors. the input has a typical offset error of 500nv (2.5v max) offset drift of 10nv/c and a noise level of 600nv rms . figure 44 (last page of this data sheet) is a complete type k thermocouple meter. the only signal conditioning is a simple surge protection network. in any thermocouple meter, the cold junction temperature sensor must be at the same temperature as the junction between the thermocouple materials and the copper printed circuit board traces. the tiny ltc2484 can be tucked neatly underneath an omega mpj-k-f thermocouple socket ensuring close thermal coupling. the ltc2484s 1.4mv/c ptat circuit measures the cold junction temperature. once the thermocouple volt- age and cold junction temperature are known, there are many ways of calculating the thermocouple temp- erature including a straight-line approximation, lookup tables or a polynomial curve ? t. calibration is per- formed by applying an accurate 500mv to the adc input derived from an lt ? 1236 reference and measuring the local temperature with an accurate thermometer as shown in figure 43. in calibration mode, the up and down buttons are used to adjust the local tempera- ture reading until it matches an accurate thermometer. both the voltage and temperature calibration are easily automated. the complete microcontroller code for this application is available on the ltc2484 product web page at: http://www.linear.com it can be used as a template for may different instruments and it illustrates how to generate calibration coef? cients for the onboard temperature sensor. extensive comments detail the operation of the program. the read_ltc2484() function controls the operation of the ltc2484 and is listed below for reference. cs sck sdo sdi f o 6 9 7 1 10 v cc 5v ltc2484 ref gnd in C in + 3 isothermal 2 c7 0.1f c8 1f 4 r2 2k r7 8k 6 2 5 4 r8 1k 5 2484 f43 26.3c type k thermocouple jack (omega mpj-k-f) 11 8 gnd in out g1 nc1m4v0 trim gnd lt1236 + figure 43. calibration setup
ltc2484 39 2484fd applications information /*** read _ ltc2484() ************************************************************ this is the function that actually does all the work of talking to the ltc2484. the spi _ read() function performs an 8 bit bidirectional transfer on the spi bus. data changes state on falling clock edges and is valid on rising edges, as determined by the setup _ spi() line in the initialize() function. a good starting point when porting to other processors is to write your own spi _ write function. note that each processor has its own way of configuring the spi port, and different compilers may or may not have built-in functions for the spi port. also, since the state of the ltc2484?s sdo line indicates when a conversion is complete you need to be able to read the state of this line through the processor?s serial data input. most processors will let you read this pin as if it were a general purpose i/o line, but there may be some that don?t. when in doubt, you can always write a ?bit bang? function for troubleshooting purposes. the ?fourbytes? structure allows byte access to the 32 bit return value: struct fourbytes // define structure of four consecutive bytes { // to allow byte access to a 32 bit int or float. int8 te0; // int8 te1; // the make32() function in this compiler will int8 te2; // also work, but a union of 4 bytes and a 32 bit int int8 te3; // is probably more portable. }; also note that the lower 4 bits are the configuration word from the previous conversion. the 4 lsbs are cleared so that they don?t affect any subsequent mathematical operations. while you can do a right shift by 4, there is no point if you are going to convert to floating point numbers - just adjust your scaling constants appropriately. *******************************************************************************/ signed int32 read _ ltc2484(char config) { union // adc _ code.bits32 all 32 bits { // adc _ code.by.te0 byte 0 signed int32 bits32; // adc _ code.by.te1 byte 1 struct fourbytes by; // adc _ code.by.te2 byte 2 } adc _ code; // adc _ code.by.te3 byte 3 output _ low(cs); // enable ltc2484 spi interface while(input(pin _ c4)) {} // wait for end of conversion. the longest // you will ever wait is one whole conversion period // now is the time to switch any multiplexers because the conversion is finished // and you have the whole data output time for things to settle. adc _ code.by.te3 = 0; // set upper byte to zero. adc _ code.by.te2 = spi _ read(config); // read first byte, send config byte adc _ code.by.te1 = spi _ read(0); // read 2nd byte, send speed bit adc _ code.by.te0 = spi _ read(0); // read 3rd byte. ?0? argument is necessary // to act as spi master!! (compiler // and processor specific.) output _ high(cs); // disable ltc2484 spi interface // clear configuration bits and subtract offset. this results in // a 2?s complement 32 bit integer with the ltc2484?s msb in the 2^20 position adc _ code.by.te0 = adc _ code.by.te0 & 0xf0; adc _ code.bits32 = adc _ code.bits32 - 0x00200000; return adc _ code.bits32; } // end of read _ ltc2484()
ltc2484 40 2484fd package description dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.115 typ 2.38 p 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 5) 0.200 ref 0.00 C 0.05 (dd10) dfn 0403 0.25 p 0.05 2.38 p 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p 0.05 (2 sides) 2.15 p 0.05 0.50 bsc 0.675 p 0.05 3.50 p 0.05 package outline 0.25 p 0.05 0.50 bsc
ltc2484 41 2484fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s . revision history rev date description page number b 11/09 revised tables 2 and 3. 15, 16 c 6/10 revised typical application added note 16 to v ih conditions in digital inputs and digital outputs section added note 16 1 4 5 d 06/11 corrected label on g39 in typical performance characteristics corrected typos in figure 4, output data rate section, and figures 35, 36, 37, and 38 in applications information section 10 18, 30, 35, 36 (revision history begins at rev b)
ltc2484 42 2484fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 0611 rev d ? printed in usa related parts typical application cs sck sdo sdi f o 6 9 7 1 10 18 17 16 15 14 13 12 11 28 27 26 25 24 23 22 21 7 6 5 4 3 2 v cc 5v ltc2484 ref gnd in C in + 3 isothermal 2 c7 0.1f c8 1f c6 0.1f 4 r2 2k 5 type k thermocouple jack (omega mpj-k-f) 5v 5v 11 8 gnd rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 ra5 ra4 ra3 ra2 ra1 ra0 v dd osc1 osc2 mclr 20 9 10 1 5v 5v y1 6mhz r1 10k d1 bat54 v ss 9 2484 f44 v ss 19 pic16f73 d7 d6 d5 d4 en rw rs r5 10k r4 10k r3 10k r6 5k 2 1 3 2 1 5v calibrate contrast gnd d0 v cc d1 d2 d3 2 s 16 character lcd display (opirex dmc162488 or similar) down up part number description comments ltc1050 precision chopper stabilized op amp no external components 5v offset, 1.6v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/c max drift ltc2400 24-bit, no latency ? adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2401/ltc2402 1-/2-channel, 24-bit, no latency ? adcs in msop 0.6ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2404/ltc2408 4-/8-channel, 24-bit, no latency ? adcs with differential inputs 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2410 24-bit, no latency ? adc with differential inputs 0.8v rms noise, 2ppm inl ltc2411/ltc2411-1 24-bit, no latency ? adcs with differential inputs in msop 1.45v rms noise, 4ppm inl, simultaneous 50hz/60hz rejection (ltc2411-1) ltc2413 24-bit, no latency ? adc with differential inputs simultaneous 50hz/60hz rejection, 800nv rms noise ltc2415/ ltc2415-1 24-bit, no latency ? adcs with 15hz output rate pin-compatible with the ltc2410 ltc2414/ltc2418 8-/16-channel 24-bit, no latency ? adcs 0.2ppm noise, 2ppm inl, 3ppm total unadjusted errors 200a ltc2420 20-bit, no latency ? adc in so-8 1.2ppm noise, 8ppm inl, pin-compatible with ltc2400 ltc2430/ltc2431 20-bit, no latency ? adcs with differential inputs 2.8v noise, ssop-16/msop package ltc2435/ltc2435-1 20-bit, no latency ? adcs with 15hz output rate 3ppm inl, simultaneous 50hz/60hz rejection ltc2440 high speed, low noise 24-bit ? adc 3.5khz output rate, 200mv noise, 24.6 enobs ltc2480 16-bit, no latency ? adc with pga/temperature sensor pin-compatible with ltc2484 ltc2482 16-bit, no latency ? adc pin-compatible with ltc2484 figure 44. complete type k thermocouple meter

▲Up To Search▲

Price & Availability of LTC2484CDDPBF

	To Download LTC2484CDDPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .